Intel Stratix 10 DX completes the Stratix 10 FPGA line
With the launch of its new Agilex 10nm FPGA lineup , Intel is simultaneously completing the formation of the already well-known and well-established Intel Stratix 10 family. The last of the varieties introduced to the market, 10 DX , is characterized by architectural innovations and closer integration with Intel Xeon server processors. Perhaps this is our last reason to talk about Intel Stratix 10, so let's do a short review of the entire family, paying special attention to the new product.
The Intel Stratix 10 line is currently the mainstream of Intel’s FPGA build, which builds numerous acceleration devices from a wide variety of manufacturers, including Intel, for example, the Intel Programmable Acceleration Card (PAC) . There are currently 5 subclasses of Stratix 10 devices:
The main technical characteristics of the whole family. The links in the table heading point to PDF documents with detailed specifications.
Now about the hero of the occasion - the Intel Stratix 10 DX family. Its distinctive features:
The Intel Stratix 10 DX is likely to be the last series in the Stratix 10 line. Further developments will be developed within the Intel Agilex family.
The Intel Stratix 10 line is currently the mainstream of Intel’s FPGA build, which builds numerous acceleration devices from a wide variety of manufacturers, including Intel, for example, the Intel Programmable Acceleration Card (PAC) . There are currently 5 subclasses of Stratix 10 devices:
- Intel Stratix 10 GX - designed to work in systems with high performance up to 10 TFLOPS, transceivers have a bandwidth of up to 28.3 Gb / s and can be used by applications of various types.
- Intel Stratix 10 SX SoC - extend the functionality of the SX series with the built-in 64-bit 4-core ARM processor Cortex-A53.
- Intel Stratix 10 TX - Provides advanced I / O capabilities by combining transceiver H- and E-tiles. E-tiles can work in two modes, allowing you to achieve speeds of up to 56 Gbit / s in PAM-4 mode and up to 28.9 Gbit / s in NRZ mode per channel.
- Intel Stratix 10 MX - combine usability and flexibility with high-performance HBM2 memory; support both H- and E-tiles of the transceiver.
- Intel Stratix 10 DX - we'll talk about them separately.
The main technical characteristics of the whole family. The links in the table heading point to PDF documents with detailed specifications.
| Intel Stratix 10 GX | Intel Stratix 10 SX | Intel Stratix 10 TX | Intel Stratix 10 MX | Intel Stratix 10 DX | |
|---|---|---|---|---|---|
| Logical Elements (KLEs) | 378 - 2,753 | 378 - 2,073 | 378-2,753 | 1,679 - 2,073 | 1,325 - 2,753 |
| Arm Cortex-A53 | - | Yes | Option | - | Option |
| Memory support | DDR4 | DDR4 | DDR4 | DDR4 / HBM2 | DDR4 / HBM2
Intel Optane DC persistent memory |
| Maximum transceiver speed
NRZ / PAM4 | 28.3 GB / s / No | 28.3 GB / s / No | 28.3 GB / s / 57.8 GB / s | 28.9 GB / s / 57.8 GB / s | 28.9 GB / s / 57.8 GB / s |
| PCI Express | PCIe Gen3x16
PCIe Gen4x16 | PCIe Gen3x16
PCIe Gen4x16 | PCIe Gen3x16
PCIe Gen4x16 | PCIe Gen3x16
PCIe Gen4x16 | PCIe Gen4x16 |
| UPI | - | - | - | - | Yes |
- The UPI (Ultra Path Interconnect) interface in combination with the next generation Intel Xeon Scalable processor will provide 37% less latency and improve overall system performance due to coherent data transfer; The maximum theoretical speed is 28 GB / s. Coherent FPGA interface - Compute Express Link (CXL) memory is implemented in Intel Agilex FPGA, the corresponding functionality in Intel Xeon will appear in 2021.
- The PCIe Gen4 x16 interface provides a theoretical speed of 32 GB / s. Thus, any application will receive a bus for data transfer twice as wide as before.
- The memory controller supports up to eight Intel Optane DC persistent memory modules per FPGA (up to 4 TB non-volatile memory).
- In addition, all the main functionality of Stratix 10 is available: 100G Ethernet, HBM2 memory, ARM Cortex-A53 processor.
The Intel Stratix 10 DX is likely to be the last series in the Stratix 10 line. Further developments will be developed within the Intel Agilex family.
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