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void StartInitClock (void) { RCC->CR |= RCC_CR_HSEON; // Enable HSE while (!(RCC->CR & RCC_CR_HSERDY)); FLASH->ACR |= FLASH_ACR_LATENCY_1; RCC->CFGR |= RCC_CFGR_PLLMUL9; // PLL mult x9 RCC->CFGR |= RCC_CFGR_PLLSRC; // Source HSE RCC->CFGR2 |= RCC_CFGR2_ADCPRE12_DIV10; // ADC source AHB/10 RCC->CR |= RCC_CR_PLLON; while((RCC->CR & RCC_CR_PLLRDY) == 0){} RCC->CFGR &= ~RCC_CFGR_SW; RCC->CFGR |= RCC_CFGR_SW_PLL; // Select source SYSCLK = PLL while((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_1) {} // Wait PLL }
ãã¥ãŒãã³ã°ã¢ã«ãŽãªãºã ã¯æ¬¡ã®ãšããã§ãïŒ å€éšã¯ãªãŒãïŒHSEïŒã«åãæ¿ããŸã->é·ç§»ãå®äºããŠã¬ãã£ãã©ã°ãèšå®ãããã®ãåŸ ã¡ãŸã->ã¯ã©ãŒãããPLLå ¥åã«ä¿¡å·ãéä¿¡ããŸã-> 8 MHzã9ã§ä¹ç®ããŸã-> 72 MHzã§åšæ³¢æ°ã10ã§é€ç®ããŸãADCãã¯ããã¯ããã«ã¯-> PLLããªã³ã«ããŸã->ãªã³ã«ãªã£ãŠã¬ãã£ãã©ã°ãèšå®ãããŸã§åŸ ã¡ãŸã-> PLLããã·ã¹ãã ãã¹ããã³ã³ã¢ã«ä¿¡å·ãéä¿¡ããŸã->åãæ¿ããå®äºãããŸã§åŸ ã¡ãŸã->å®äºããŸãã
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RCC->CFGR3 |= RCC_CFGR3_HRTIM1SW_PLL; RCC->APB2ENR |= RCC_APB2ENR_HRTIM1EN;
HRTIMãPLLããã¯ããã¯ãããããã«æå®ããå¿ èŠããããx2ä¹ç®åšã¯ããã©ã«ãã§ãã§ã«æå¹ã«ãªã£ãŠããŸãã 次ã«ãHRTIMã®ã¯ããã¯ããªã³ã«ããŸãããããæåã®æ©èœã§ããã¿ã€ããŒã¯PLLããã¯ããã¯ãäŸçµŠãããŠããããšãããããŸãããAPB2ã®å Žåã¯ãªã³ã«ããŸãã ããã¯å®å šã«è«ççã§ã¯ãããŸããããCMSISã䜿çšãããã¡ã€ã«ã§ã¯ç°¡åã«æ€çŽ¢ã§ããŸãã
RCC->AHBENR |= RCC_AHBENR_GPIOAEN; GPIOA->MODER &= ~GPIO_MODER_MODER8; GPIOA->MODER |= GPIO_MODER_MODER8_1; // Alternative PP GPIOA->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR8; // Very high speed GPIOA->MODER &= ~GPIO_MODER_MODER9; GPIOA->MODER |= GPIO_MODER_MODER9_1; GPIOA->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR9; GPIOA->AFR[1] |= 0xDD; // PA8 and PA9 - AF13
PA8ãšPA9ã¯ã¿ã€ããŒAã®åºåã§ãç§ã®ã¢ãžã¥ãŒã«ã§ã¯ãã£ã³ãã«1ã«é²ã¿ãŸããããã¯å³ãšãã³é åã§ç¢ºèªã§ããŸãã èã¯ã代æ¿æ©èœãåããããã·ã¥ãã«ãšããŠæ§æãããŠãããäž¡æ¹ã®èã®æ©èœèªäœã®æ°ã¯13çªç®ã§ãã æ倧GPIOåšæ³¢æ°ã«èª¿æŽããããšãéèŠã§ããããããªããšããã¯ãŒãšã¬ã¯ãããã¯ã¹ã«ãšã£ãŠéåžžã«éèŠãªãä¿¡å·ã®ããã³ããšãã©ãŒã«ã®äžå¯è§£ãªããããã³ã°ãçºçããŸãã
HRTIM1->sCommonRegs.DLLCR |= HRTIM_DLLCR_CAL | HRTIM_DLLCR_CALEN; while ((HRTIM1->sCommonRegs.ISR & HRTIM_ISR_DLLRDY) == RESET);
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HRTIM1->sTimerxRegs[0].PERxR = PeriodTimerA; // Period for timer A HRTIM1->sTimerxRegs[0].CMP1xR = 0; // Duty for timer A
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// Deadtime enable HRTIM1->sTimerxRegs[0].OUTxR |= HRTIM_OUTR_DTEN; // Tdtg = 6.94 ns HRTIM1->sTimerxRegs[0].DTxR |= HRTIM_DTR_DTPRSC_0 | HRTIM_DTR_DTPRSC_1; // Deadtime rising = 15*Ttg = 104 ns HRTIM1->sTimerxRegs[0].DTxR |= HRTIM_DTR_DTR_0 | HRTIM_DTR_DTR_1 | HRTIM_DTR_DTR_2 | HRTIM_DTR_DTR_3; // Deadtime falling = 15*Ttg = 104 ns HRTIM1->sTimerxRegs[0].DTxR |= HRTIM_DTR_DTF_0 | HRTIM_DTR_DTF_1 | HRTIM_DTR_DTF_2 | HRTIM_DTR_DTF_3; HRTIM1->sTimerxRegs[0].DTxR |= HRTIM_DTR_DTFSLK | HRTIM_DTR_DTRSLK;
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// Samples in middle of ON time HRTIM1->sTimerxRegs[0].CMP2xR = PeriodTimerA / 10; // ADC trigger 1 update: Timer A HRTIM1->sCommonRegs.CR1 |= HRTIM_CR1_ADC1USRC_0; // ADC trigger 1 event: Timer A compare 2 HRTIM1->sCommonRegs.ADC1R |= HRTIM_ADC1R_AD1TAC2;
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// Enable output PWM for TA1 and TA2 HRTIM1->sCommonRegs.OENR |= HRTIM_OENR_TA1OEN | HRTIM_OENR_TA2OEN; // Continuous mode HRTIM1->sTimerxRegs[0].TIMxCR |= HRTIM_TIMCR_CONT; // Period for master timer HRTIM1->sMasterRegs.MPER = 65000; // Enable counter for Master and timer A HRTIM1->sMasterRegs.MCR |= HRTIM_MCR_MCEN | HRTIM_MCR_TACEN;
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void SetDutyTimerA (uint16_t duty) { HRTIM1->sTimerxRegs[0].CMP1xR = duty; }
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// f = 102,4 kHz #define PeriodTimerA ((uint16_t)45000) void InitHRPWM (void) { RCC->CFGR3 |= RCC_CFGR3_HRTIM1SW_PLL; RCC->APB2ENR |= RCC_APB2ENR_HRTIM1EN; /************************************************ * Setting GPIO ***********************************************/ RCC->AHBENR |= RCC_AHBENR_GPIOAEN; // Alternative PP GPIOA->MODER &= ~GPIO_MODER_MODER8; GPIOA->MODER |= GPIO_MODER_MODER8_1; // Very high speed GPIOA->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR8; GPIOA->MODER &= ~GPIO_MODER_MODER9; GPIOA->MODER |= GPIO_MODER_MODER9_1; GPIOA->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR9; // PA8 and PA9 - AF13 GPIOA->AFR[1] |= 0xDD; /************************************************ * Setting timer A ***********************************************/ HRTIM1->sCommonRegs.DLLCR |= HRTIM_DLLCR_CAL | HRTIM_DLLCR_CALEN; while ((HRTIM1->sCommonRegs.ISR & HRTIM_ISR_DLLRDY) == RESET); // Period for timer A HRTIM1->sTimerxRegs[0].PERxR = PeriodTimerA; // Duty for timer A HRTIM1->sTimerxRegs[0].CMP1xR = 0; // Deadtime enable HRTIM1->sTimerxRegs[0].OUTxR |= HRTIM_OUTR_DTEN; // Tdtg = 6.94 ns HRTIM1->sTimerxRegs[0].DTxR |= HRTIM_DTR_DTPRSC_0 | HRTIM_DTR_DTPRSC_1; // Deadtime rising = 15*Ttg = 104 ns HRTIM1->sTimerxRegs[0].DTxR |= HRTIM_DTR_DTR_0 | HRTIM_DTR_DTR_1 | HRTIM_DTR_DTR_2 | HRTIM_DTR_DTR_3; // Deadtime falling = 15*Ttg = 104 ns HRTIM1->sTimerxRegs[0].DTxR |= HRTIM_DTR_DTF_0 | HRTIM_DTR_DTF_1 | HRTIM_DTR_DTF_2 | HRTIM_DTR_DTF_3; HRTIM1->sTimerxRegs[0].DTxR |= HRTIM_DTR_DTFSLK | HRTIM_DTR_DTRSLK; // Event forces the output to active state for TA1 HRTIM1->sTimerxRegs[0].SETx1R |= HRTIM_SET1R_PER; // Event forces the output to inactive state for TA1 HRTIM1->sTimerxRegs[0].RSTx1R |= HRTIM_RST1R_CMP1; /************************************************ * ADC trigger intialization (with CMP2 event) ************************************************/ // Samples in middle of ON time HRTIM1->sTimerxRegs[0].CMP2xR = PeriodTimerA / 10; // ADC trigger 1 update: Timer A HRTIM1->sCommonRegs.CR1 |= HRTIM_CR1_ADC1USRC_0; // ADC trigger 1 event: Timer A compare 2 HRTIM1->sCommonRegs.ADC1R |= HRTIM_ADC1R_AD1TAC2; /************************************************ * HRTIM start ***********************************************/ // Enable output PWM for TA1 and TA2 HRTIM1->sCommonRegs.OENR |= HRTIM_OENR_TA1OEN | HRTIM_OENR_TA2OEN; // Continuous mode HRTIM1->sTimerxRegs[0].TIMxCR |= HRTIM_TIMCR_CONT; // Period for master timer HRTIM1->sMasterRegs.MPER = 65000; // Enable counter for Master and timer A HRTIM1->sMasterRegs.MCR |= HRTIM_MCR_MCEN | HRTIM_MCR_TACEN; } void SetDutyTimerA (uint16_t duty) { HRTIM1->sTimerxRegs[0].CMP1xR = duty; }
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void InitBasicADC (void) { RCC->AHBENR |= RCC_AHBENR_ADC12EN; RCC->AHBENR |= RCC_AHBENR_GPIOCEN; /************************************************ * Calibration ***********************************************/ ADC2->CR &= ~ADC_CR_ADVREGEN; ADC2->CR |= ADC_CR_ADVREGEN_0; // Vref enable Delay(10); ADC2->CR &= ~ADC_CR_ADCALDIF; ADC2->CR |= ADC_CR_ADCAL; // Start calibration while (ADC2->CR & ADC_CR_ADCAL); // Wait end calibration /************************************************ * Select event trigger and channel ***********************************************/ // Enable start conversion external trigger ADC2->CFGR |= ADC_CFGR_EXTEN_0; // Event 7 - HRTIM ADC2->CFGR |= ADC_CFGR_EXTSEL_0 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_2; // Select ADC2 channel IN5 ADC2->SQR1 |= ADC_SQR1_SQ1_0 | ADC_SQR1_SQ1_2; // Length regular ADC channel = 1 ADC2->SQR1 &= ~ADC_SQR1_L; ADC2->IER |= ADC_IER_EOCIE; // Interrupt enable NVIC_EnableIRQ(ADC1_2_IRQn); // enable interrupt ADC1 and ADC2 /************************************************ * Start ADC ***********************************************/ ADC2->CR |= ADC_CR_ADEN; // Enable ADC2 Delay(10); ADC2->CR |= ADC_CR_ADSTART; }
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void ADC1_2_IRQHandler (void) { ADC2->ISR |= ADC_ISR_EOC; adcResult = ADC2->DR; if (adcResult > 2480) { dutyControl = dutyControl - 10; } else { dutyControl = dutyControl + 10; } SetDutyTimerA(dutyControl); }
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