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---------------------------------------------------------------------------------------------------------- -- Company: House -- Engineer: AlexanderS -- -- Create Date: 13/06/2012 -- Modification Date: --/--/---- -- Module Name: manag_pc -- Project Name: - -- Version: v.1.1 -- Description: PWR , WOL -- / PWR SW ---------------------------------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --use IEEE.STD_LOGIC_SIGNED.ALL; use IEEE.NUMERIC_STD.ALL; --use IEEE.MATH_REAL.ALL; --library UNISIM; --use UNISIM.VComponents.ALL; entity project is GENERIC ( ---------- ---------- CLOCK : integer := 100000000 -- , [; 1000] ); Port ( ---------- ---------- led: out std_logic_vector(7 downto 0) :=(others=>'0'); f0: in std_logic_vector(9 downto 0) :=(others=>'1'); f1: in std_logic_vector(9 downto 0) :=(others=>'1'); f2: out std_logic_vector(9 downto 0) :=(others=>'0'); ---------- ---------- CLK: in std_logic :='0' -- ( CLOCK) ); end project; architecture Behavioral of project is signal df : std_logic_vector(5 downto 0) :=(others=>'0'); signal sw_lock : std_logic :='0'; signal hl : std_logic_vector(7 downto 0) :=(others=>'0'); signal PWR_BUT1, WOL1, PWRB_on, WOL, lock : std_logic :='0'; signal PWR_BUT2, WOL2 : std_logic :='1'; signal st : integer range 3 downto 0 :=0; signal sec0125, sec025, sec05, sec, sec2, min, hour, day, res_time : std_logic :='0'; signal time_s, time_m : std_logic_vector(5 downto 0) :=(others=>'0'); signal time_h : std_logic_vector(4 downto 0) :=(others=>'0'); COMPONENT gen_time is -- GENERIC ( CLOCK : integer := 100000000 ); Port ( ---------- ---------- sec0125: out std_logic :='0'; sec025: out std_logic :='0'; sec05: out std_logic :='0'; sec2: out std_logic :='0'; sec: out std_logic :='0'; time_s : out std_logic_vector(5 downto 0) :=(others=>'0'); min: out std_logic :='0'; time_m : out std_logic_vector(5 downto 0) :=(others=>'0'); hour: out std_logic :='0'; time_h : out std_logic_vector(4 downto 0) :=(others=>'0'); day: out std_logic :='0'; ---------- ---------- RES: in std_logic :='0'; CLK: in std_logic :='0' ); end COMPONENT; begin Inst_gen_time: gen_time -- GENERIC MAP( CLOCK => 100000000 ) Port MAP ( sec0125 => sec0125, sec025 => sec025, sec05 => sec05, sec => sec, sec2 => sec2, time_s => time_s, min => min, time_m => time_m, hour => hour, time_h => time_h, day => day, RES => res_time, CLK => CLK ); res_time <= '0'; ---- BEGIN - Process(CLK) begin if (CLK'Event) and (CLK='1') then if (sw_lock = '0') then if (f0(0) = '0') or (f1(0) = '0') then sw_lock <= '1'; end if; df(0) <= not f0(0); hl(6) <= f0(0); df(1) <= not f1(0); hl(7) <= f1(0); elsif (sec0125 = '1') then sw_lock <= '0'; end if; end if; if (df(2) = '1') then f2 <= (others=>'1'); else f2 <= (others=>'0'); end if; led <= hl; end if; end process; ----- END - --- BEGIN process(CLK) begin if (CLK'event and CLK = '1') then PWR_BUT1 <= df(0); PWR_BUT2 <= not PWR_BUT1; WOL1 <= df(1); WOL2 <= not WOL1; if ((PWR_BUT1 = '1') and (PWR_BUT2 = '1')) then -- PWRB_on <= '1'; elsif ((PWR_BUT1 = '0') and (PWR_BUT2 = '0')) then -- PWRB_on <= '0'; elsif ((WOL1 = '1') and (WOL2 = '1')) then WOL <= '1'; else WOL <= '0'; end if; -- WOL if (PWRB_on = '1') and (lock = '0') then -- df(2) <= '1'; hl(0) <= not hl(0); lock <= '1'; elsif (PWRB_on = '0') and (lock = '1') then -- df(2) <= '0'; lock <= '0'; else -- WOL case st is when 0 => if (WOL = '1') then st <= st + 1; end if; -- when 1 => df(2) <= '1'; if (sec025 = '1') then st <= st + 1; end if; when 2 => if (sec025 = '1') then st <= st + 1; end if; when 3 => hl(0) <= not hl(0); df(2) <= '0'; st <= 0; when others => null; end case; end if; end if; end process; --- END end Behavioral;

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