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RCC->APB1ENR|= RCC_APB1ENR_TIM2EN; RCC->APB2ENR|= RCC_APB2ENR_IOPAEN;
ããã2è¡ã§ã¯ãããããAPB1ENRããã³APB2ENRã¬ãžã¹ã¿ ïŒAPB1ããã³APB2ããªãã§ã©ã«ã¯ããã¯ã€ããŒãã«ã¬ãžã¹ã¿ïŒã®TIM2ENãããïŒã¿ã€ããŒ2ã«ã¯ããã¯ãäŸçµŠããïŒããã³IOPAEN ïŒã¯ããã¯ãããŒãAã«éä¿¡ããïŒãèšå®ããŸãã
ãããŠãããäžã€éèŠãªããšããããŸãïŒ
GPIOA->CRL |=GPIO_CRL_MODE2; GPIOA->CRL &=~GPIO_CRL_CNF2_0; GPIOA->CRL |=GPIO_CRL_CNF2_1; GPIOA->CRL |=GPIO_CRL_MODE3; GPIOA->CRL &=~GPIO_CRL_CNF3_0; GPIOA->CRL |=GPIO_CRL_CNF3_1;
äž¡æ¹ã®ãã³PA2ãPA3ãåºåã«èšå®ããŸãããå®éã«ã¯ãSTMã§ã¯GPIOåäœã¢ãŒãã«åé¢ããããŸãã ããã°ã©ã ã§ãã³ã®ç¶æ ã1ãŸãã¯0ã«èšå®ããå Žåã¯ãåºåããã·ã¥ãã«ãŸãã¯åºåãªãŒãã³ãã¬ã€ã³ã®åäœã¢ãŒããéžæããå¿ èŠããããŸãã 代æ¿æ©èœåã®ãã³é 眮ã»ã¯ã·ã§ã³ã®ç¹å®ã®ã³ã³ãããŒã©ãŒã¢ãã«ã®ããŒã¿ã·ãŒãã§æå®ãããŠããã¿ã€ããŒãªã©ã®åšèŸºããã€ã¹ããã®ç¶æ ãå¶åŸ¡ãããšæ³å®ãããå Žåã代æ¿æ©èœããã·ã¥ãã«ãŸãã¯ä»£æ¿æ©èœãªãŒãã³ãã¬ã€ã³ã¢ãŒããéžæããŸãã ã¢ãŒãã誀ã£ãŠèšå®ãããšãã¿ã€ããŒã¯PWMä¿¡å·ãåºåã§ããªããªããŸãã
ã¬ãžã¹ã¿ã«ã€ããŠç°¡åã«èª¬æãããšãåããŒãã«ã¯ãæ¬è³ªçã«åã2ã€ã®å¶åŸ¡ã¬ãžã¹ã¿CRLãšCRHãå«ãŸããŠããŸãã CRLã§ã¯ããã³èšå®0-7ãCRH-8-15ã«ä¿åãããŸãã åãã³ã«ã¯4ããããããããã®ãã¡2ã€ã¯MODE㧠ãå ¥åºåã®æ¹åãšåºåã¢ãŒãã§ã®ãã³ã®æ倧ã¹ã€ããã³ã°åšæ³¢æ°ã®å¶éãæ åœããä»ã®2ã€CNFã¯åãåäœã¢ãŒããä¿åããŸãã
åèšã§ãããã«ãã8ã€ã®å¯èœãªãã³ç¶æ ãåŸãããŸãã
- å ¥åããã«ãããŠããªãïŒ MODE [1ïŒ0] = 00ã CNF [1ïŒ0] = 01ïŒ
- é»æºã«åŒã蟌ãŸããå ¥åïŒ MODE [1ïŒ0] = 00ã CNF [1ïŒ0] = 10ã1ãããŒãåºåã«éä¿¡ãããŸãïŒ
- å ¥åãã°ã©ã³ãã«ãã«ãããŸãïŒ MODE [1ïŒ0] = 00ã CNF [1ïŒ0] = 10ã0ãããŒãåºåã«éä¿¡ãããŸãïŒ
- ã¢ããã°å ¥åïŒ MODE [1ïŒ0] = 00ã CNF [1ïŒ0] = 00ïŒ-ãã®å Žåãã·ã¥ãããå ¥åããªã¬ãŒãšãã«ã¢ããæµæããªãã«ãªãããã³ã¯Zç¶æ ã«ãªããŸãã
- åºåããªãŒãã³ãã¬ã€ã³GPIOïŒ MODE [1ïŒ0]ïŒ= 00ã CNF [1ïŒ0] = 01ïŒ
- çµäºãããã·ã¥ãã«GPIOïŒ MODE [1ïŒ0]ïŒ= 00ã CNF [1ïŒ0] = 00ïŒ
- åºåãåšèŸºæ©åšã«ãã£ãŠå¶åŸ¡ããããªãŒãã³ãã¬ã€ã³ïŒ MODE [1ïŒ0]ïŒ= 00ã CNF [1ïŒ0] = 11ïŒ
- çµäºãåšèŸºæ©åšã«ãã£ãŠå¶åŸ¡ãããããã·ã¥ãã«ïŒ MODE [1ïŒ0]ïŒ= 00ã CNF [1ïŒ0] = 10ïŒ
ãã®ç®çã®ããã«ãããã·ã¥ãã«ã¢ãŒãã§åšèŸºæ©åšã«ãã£ãŠå¶åŸ¡ãããåºåçšã«æ§æããããã³ãå¿ èŠã§ãã ãããã£ãŠã MODE2 [1ïŒ0]ããã³MODE3 [1ïŒ0]ãããã®å€ã00以å€ã®å€ãããšãã°11ã«èšå®ãã CNF2 [1ïŒ0]ããã³CNF3 [1ïŒ 0]-å€10
æ®ãã®åšèŸºã¬ãžã¹ã¿ã®è©³çŽ°ã«ã€ããŠã¯ãRM0008ã STM32F1xxãªãã¡ã¬ã³ã¹ããã¥ã¢ã«ãåç §ããŠãã ãã ã ã€ãŸãã IDRããã³ODRã¬ãžã¹ã¿ã«ã¯ããŒãã®ãã³ã®å ¥åå€ãšåºåå€ãå«ãŸãã BSRRã¯ODRã®ãããã®ãªã»ããã®ã¿ãèšå®ãã BRRã¯ã¢ãããã¯ã«å®è¡ããŸããã€ãŸãããã®æäœã¯1ã€ã®ãã¹ãµã€ã¯ã«ã§å®è¡ãããŸããå²ã蟌ã¿ãäžæã§ããŸããã æåŸã®ããŒãã¬ãžã¹ã¿LCKRã§ã¯ããã³å€ããããã¯ãããŠããªã»ãããããŸã§ãã³å€ãå€æŽãããªãããã«ããããšãã§ããŸã ã
次ã«ãã¿ã€ããŒãèšå®ããŸãã ã€ã³ã¿ãŒãããã§èŠã€ãã£ãããŒã¿ã«ãããšãPWMåšæã¯20ã60 Hzããéžæããå¿ èŠããããŸãããçŽ1 msã®å¹ ã®ãã«ã¹ã¯0床ã1.5 ms-90床ã2 ms-180ãæå³ããŸãã
PWM容éã«é¢ããŠã¯ãååãšããŠãã©ãã§ãéžæã§ããŸããããµãŒãã®äœçœ®æ±ºã粟床ã¯äŸç¶ãšããŠæéã§ããããã12ããããéžæããŸããã ãŸãã12ãããã¯ããã«ã¹å¹ ã®0ããªç§ãããã®åšæã«çããå€ãžã®å€åãè¡šãããµãŒããŒã¯1ãã2ããªç§ã®ç¯å²ã§åäœããããã12ããããã¹ãŠãèªç±ã«äœ¿ããããã§ã¯ãªãããšãèŠããŠããå¿ èŠããããŸãã ä»åŸãå®éšã®çµæã次ã®ãã©ã¡ãŒã¿ã«å°éãããšèšããŸãã
- PWMä¿¡å·åšæ³¢æ°ïŒ35 Hzã ç§ã¯ãããåã«å¹³åå€ãšããŠéžæããŸããããµãŒããŒã¯30 Hzãš50 Hzã®äž¡æ¹ã§å®å®ããŠåäœããŸãã
- 0床ã«å¯Ÿå¿ãããã«ã¹å¹ ïŒçŽ0.5ããªç§ããã ãã0.5以äžãéžæãããšããµãŒããŒãã¯ã©ãã¯ãéå§ããŸãã ããã¯ãç©ççãªå転èœåã®å¢çã«äœçœ®ããŠããŸãã ãããã£ãŠãããå®å®ããåäœã®ããã«ãçŽ0.56 msã®å¹ ã®ãã«ã¹ã䜿çšããŸã
- 180床ã«å¯Ÿå¿ãããã«ã¹å¹ ïŒçŽ2.3 msããŒãå転ã®å Žåãšåãç¶æ³-å¢çããå°ã倧ããèšå®ãããšãã¯ã©ãã¯ãçºçãå§ããŸãã
35 Hzã®PWMåšæ³¢æ°ãš12ãããã®å解èœãéžæãããšãæéå šäœã§4096ã®å€ãåŸãããŸãã0x50ã¯å¹ 0.56 msã«å¯Ÿå¿ãã0x150ã¯2.34 msã®å¹ ã«å¯Ÿå¿ããŸãã
ãããã£ãŠãçŽ180床ã§256åã®å€ãååŸããŸããããã¯ããµã³ãã«ãããçŽ40ã¢ãŒã¯åã®é¢æ£æ§ãæå³ããŸãã å¿ èŠã«å¿ããŠãå®éšãç¶è¡ããŠããã©ã€ããäœçœ®æ±ºããå®è¡ã§ããæ£ç¢ºãªå¢çå€ãšç²ŸåºŠã決å®ã§ããŸãã
ãã®ããã次ã®ã³ãŒããã©ã°ã¡ã³ãã¯ã¿ã€ããŒ2ãèšå®ããŸãã
TIM2->PSC = 0x00A7; TIM2->ARR = 0x0FFF; TIM2->CCR3 = 0x050; TIM2->CCR4 = 0x0150;
ããã§ã¯ãã¹ãŠãéåžžã«ç°¡åã§ããPSCã¬ãžã¹ã¿ïŒããªã¹ã±ãŒã©ãŒïŒãããªãã£ãã€ããŒãæ åœãã ARRã¬ãžã¹ã¿ïŒèªåãªããŒãã¬ãžã¹ã¿ïŒãã¿ã€ããŒãå»ãæ倧å€ãæ åœããŸãã ARRã«æ°å€0xFFFãèšå®ãããšã12ãããã¿ã€ããŒãåŸãããŸãããã®èšç®åšæã¯ãã¯ããã¯åšæ³¢æ°ã0xFFFã§å²ã£ãå€ãã€ãŸã24000000/4096 = 5859ã§ãããã®å€ãå¥ã®0xA7ã§é€ç®ãããšã5859/167 = 35 Hzã«ãªããŸãã
CCR3ããã³CCR4 ïŒãã£ããã£æ¯èŒã¬ãžã¹ã¿ïŒã¬ãžã¹ã¿ã®å€ã¯ãã«ãŠã³ã¿ãŒå€ãšæ¯èŒãããå®éã®PââWMãã¥ãŒãã£ãµã€ã¯ã«ãèšå®ããŸãã 次ã«ãã¿ã€ããŒã¢ãŒããèšå®ããŸãã
TIM2->CCMR2 |= TIM_CCMR2_OC3M_1|TIM_CCMR2_OC3M_2; TIM2->CCER |= TIM_CCER_CC3E; TIM2->CCMR2 |= TIM_CCMR2_OC4M_1|TIM_CCMR2_OC4M_2; TIM2->CCER |= TIM_CCER_CC4E; TIM2->CR1 |= TIM_CR1_CEN;
ç¶æ³ã¯ãããŒãèšå®ã¬ãžã¹ã¿ãšåãã§ãã2ã€ã®ãã£ããã£ããã³æ¯èŒã¢ãŒãã¬ãžã¹ã¿ã¬ãžã¹ã¿ã CCMR1 ã CCMR2ã¯ããããããã£ãã«1ã2ãããã³3,4ã®åäœã¢ãŒããæ åœããŸãã å€ãã®èšå®ããããŸããããã®ç¹ã«ã€ããŠã¯ãªãã¡ã¬ã³ã¹ããã¥ã¢ã«ãèªãããšããå§ãããŸãã æŠèŠã®å Žå-ã¬ãžã¹ã¿ã¯ãã¿ã€ããŒã§ã®PWMä¿¡å·ã®ãã£ããã£ãšãã®åºåã«é¢é£ããã¢ãŒããæ åœããŸãã CCxSãããïŒxã¯ãã£ãã«çªå·ïŒã¯ããã®ãã£ãã«ãå ¥åãŸãã¯åºåã«æ§æããŸãã åºåã¢ãŒãã¯ããã©ã«ãã§ãªã³ã«ãªã£ãŠããããããããã«ã¯è§ŠããŸããã èšå®ãããOCxMããã[2ïŒ0]ã¯ããã£ãã«ãã«ãŠã³ã¿å€ã®æ¯èŒã«å¿çããæ¹æ³ãæ åœããŸãïŒã«ãŠã³ã¿å€ã¯ãã¬ãžã¹ã¿ã«ä¿åãããŸãïŒ
TIM2-> CNT ïŒããã³CCRxã¬ãžã¹ã¿ã åèš8ã€ã®ãªãã·ã§ã³ãå¯èœã§ãã
- 000-æ¯èŒã¯åºåã«åœ±é¿ããŸãã
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- 010-ãã£ãã«ã®åºåã®å€ãäžèŽããå Žåã0ãèšå®ãããŸã
- 011-å€ãäžèŽãããšãåºåä¿¡å·ã¯å察ã®ç¶æ ã«åãæ¿ãããŸã
- 100-åºåã¯åžžã«0ã«èšå®ãããŸã
- 101-åºåã¯åžžã«1ã«èšå®ãããŸã
- 110-PWMãã¢ãŒã1ãéåžžïŒ CCRxã®å€< CNT ãåºå1ããã以å€ã¯0ïŒ
- 111-PWMãã¢ãŒã2ãéïŒ CCRxã®å€< CNT ãåºå0ããã以å€ã¯1ïŒ
ã¢ãŒãã110ãéåžžã®PWMã«èšå®ããŸãã CCER ïŒãã£ããã£/æ¯èŒæå¹åã¬ãžã¹ã¿ïŒã¬ãžã¹ã¿ã®CCxEããããèšå®ããããšãå¿ããªãã§ãã ãã-察å¿ãããã£ãã«ã®åºåãæå¹ã«ããŸãã
ãã®åŸã CR1ã¬ãžã¹ã¿ïŒå¶åŸ¡ã¬ãžã¹ã¿1ïŒã®CENããããèšå®ããŠãã¿ã€ããŒå šäœããªã³ã«ããŸãã
ããã§ãPWMãçµäºãããªã·ãã¹ã³ãŒãã®ç»é¢ã«çŸããç»åã衚瀺ããããµãŒããå察ã®äœçœ®ã«ãªããŸãã å¿ èŠã«å¿ããŠããã¹ãŠã®åæååŸã«ãã¬ãŒã«ãŒãé 眮ããCaleã®çµã¿èŸŒã¿ããŒã«ã䜿çšããŠå€ãå€æŽããŠãããã»ããµãšåšèŸºæ©åšã®ã¬ãžã¹ã¿ã衚瀺ããã³ç·šéãããªã·ãã¹ã³ãŒãç»é¢ã®ä¿¡å·ãã¥ãŒãã£ãµã€ã¯ã«ã®å€åãšãµãŒãã·ã£ããã®äœçœ®ãããã«èŠ³å¯ã§ããŸãã
ããŠãç¬åŠã®ããã«ãããã°ã©ã ãããå°ãé¢çœãããŸããã-è§åºŠã®å€ãæ倧ããæå°ã«å€æŽããŸãã ãããè¡ãã«ã¯ãARM Cortex-M3ã®ã³ã¢ã«ããããSysTickã¿ã€ããŒãå«ãŸããŠããããšãæãåºããŠãã ãããããã¯ããªãã¬ãŒãã£ã³ã°ã·ã¹ãã ãå®è£ ããå Žåãªã©ãã°ããŒãã«ãªåæãšå²ã蟌ã¿ã®çæçšã«èšèšããã24ãããã¿ã€ããŒã§ãã ã¿ã€ããŒã¯ã SysTick_ConfigïŒuint32_t TicksïŒé¢æ°ã䜿çšããŠåæåãããŸãã ãã®æ©èœã¯CMSISã®äžéšã§ãããæšæºåšèŸºæ©åšã©ã€ãã©ãªããããåºæ¬ãã§ããããã䜿çšããŸãã
ãã®é¢æ°ã®å éšãèå³æ·±ãå Žåã¯ãCMSISã®è žå ã®èª¬æã«é²ãããšãã§ããŸãïŒãã¡ã€ã«core_cm3.h ãè¡1137ïŒã äžè¬ã«ããã®é¢æ°ã¯ç¹ã«è€éãªããšã¯äœããããæž¡ãããTicksãã©ã¡ãŒã¿ãŒã®å€ããã§ãã¯ããŠ24ããããè¶ ããŠãããã©ããã確èªããŠãããã¬ãžã¹ã¿ãŒãèšå®ããŸãã
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⢠SysTick-> VAL at 0ã¯ãçŸåšã®ã«ãŠã³ã¿ãŒå€ã§ã
â¢ãããCLKSOURCE ã TICKINT ã ENABLEã¬ãžã¹ã¿SysTick-> CTRL in 1ã
CLKSOURCEããã㯠ãã¿ã€ããŒã®ã¯ããã¯ãœãŒã¹ãæ åœããŸãã äžè¬çã«ãã³ã¢ã®ä»æ§ã§ã¯ã2çªç®ã®ä¿¡å·ãã©ã®ãããªãã®ã§ããããèšè¿°ãããŠããªãããïŒæåã®ä¿¡å·ã¯åžžã«ã·ã¹ãã ã¯ããã¯ã«æ¥ç¶ãããŸãïŒããã®ãããã®åœ±é¿ã¯ã¡ãŒã«ãŒããšã«å€ããå¯èœæ§ããããŸãã STM32Fã§ã¯ã2çªç®ã®ãããã¯ä¿¡å·ã¯SystemCoreClock / 8ã«æ¥ç¶ãããŸãã ãããã1ã«èšå®ããããšã«ãããã·ã¹ãã ã¯ããã¯ã®ãœãŒã¹ãéžæããŸãã
TICKINTãããã¯ãã¿ã€ããŒãªãŒããŒãããŒã«ããå²ã蟌ã¿ïŒãŸãã¯å®è¡ïŒã®çæãæå¹ã«ããŸãã 1ã«èšå®ããããããã¹ãŠãéå§ãããŸããïŒ
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説æããã¢ã¯ã·ã§ã³ã«å ããŠã SysTick_Configé¢æ°ã¯ãåªå 床ã0ããå§ãŸãïŒå®éã«ã¯-3ã§ããã0æªæºã®åªå 床ã¯èšå®ã§ããªãïŒãããå²ã蟌ã¿åªå 床ã240ã«èšå®ããŸãã
çŸåšã®PWMèšå®ã¯0ã180床ã§256ã¹ããããæå³ãããããã¿ã€ããŒãåšæ³¢æ°ã«èšå®ããŸãã
SystemCoreClock /256ããã®ãµãŒããã¹ã¯1ç§ã§ééããŸãã
SysTick_Config(SystemCoreClock/256);
SystemCoreClockå®æ°ã¯ ã system_stm32f10x.cã® 114è¡ç®ã§å®çŸ©ãããŠããã1ç§ã®ã³ã¢ã¯ããã¯æ°ãã€ãŸã24000000ã«çãããªããŸãã
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int8_t ChannelDir[2]={1,-1}; volatile uint16_t *DutyCycle[2]={TIM2->CCR3,&TIM2->CCR4}; void SysTick_Handler() { uint8_t i; for(i=0;i<2;i++) { *DutyCycle[i]+=ChannelDir[i]; if(*DutyCycle[i]<0x50) ChannelDir[i]=1; if(*DutyCycle[i]>0x150) ChannelDir[i]=-1; } }
2ã€ã®ãã£ãã«ããããããäž¡æ¹ã®ãã£ãã«ãåæã«æåŸ ãããã³ãã©ãŒãäœæããŸãã åäžã®ã¡ã¢ãªç©ºéããããããéåžžã®ã¡ã¢ãªã»ã«ãšããŠã¬ãžã¹ã¿ã«èªç±ã«ã¢ã¯ã»ã¹ã§ãããããããã«2ã€ã®ã¬ãžã¹ã¿ãžã®ãã€ã³ã¿ã宣èšããŸãã
volatile uint16_t *DutyCycle[2]={&TIM2->CCR3,&TIM2->CCR4};
ãã®åŸããã¹ãŠãéåžžã«ç°¡åã§ã-ãµã€ã¯ã«ã2ã€ã®ãã£ã³ãã«ã«ç·šæããçŸåšã®ãã¥ãŒãã£ãµã€ã¯ã«å€ã«1ãå ç®ãŸãã¯æžç®ãïŒæ¹åã«å¿ããŠïŒããµãŒãã極端ãªäœçœ®ã«éãããšæ¹åãå€æŽããŸãã
ãã¹ãŠãã³ã³ãã€ã«ããŸãããã¹ãŠãæ£ããè¡ãããå Žåãäžã®ãããªã§çŽ¹ä»ãããããªå æ¯ãã楜ãã¿ããã ããŸãã
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#include "stm32f10x.h" int8_t ChannelDir[2]={1,-1}; volatile uint16_t *DutyCycle[2]={&TIM2->CCR3,&TIM2->CCR4}; void SysTick_Handler() { uint8_t i; for(i=0;i<2;i++) { *DutyCycle[i]+=ChannelDir[i]; if(*DutyCycle[i]<0x50) ChannelDir[i]=1; if(*DutyCycle[i]>0x150) ChannelDir[i]=-1; } } int main() { RCC->APB2ENR |= RCC_APB2ENR_IOPAEN; RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; GPIOA->CRL |=GPIO_CRL_MODE2; GPIOA->CRL &=~GPIO_CRL_CNF2_0; GPIOA->CRL |=GPIO_CRL_CNF2_1; GPIOA->CRL |=GPIO_CRL_MODE3; GPIOA->CRL &=~GPIO_CRL_CNF3_0; GPIOA->CRL |=GPIO_CRL_CNF3_1; TIM2->PSC = 0x00A7; TIM2->ARR = 0x0FFF; TIM2->CCR3 = 0x050; TIM2->CCR4 = 0x0150; TIM2->CCMR2 |= TIM_CCMR2_OC3M_1|TIM_CCMR2_OC3M_2; TIM2->CCER |= TIM_CCER_CC3E; TIM2->CCMR2 |= TIM_CCMR2_OC4M_1|TIM_CCMR2_OC4M_2; TIM2->CCER |= TIM_CCER_CC4E; TIM2->CR1 |= TIM_CR1_CEN; SysTick_Config(SystemCoreClock/256); while(1); }
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