Intel Tremont - New Microarchitecture for Energy Efficiency

Almost like in the story with all the famous gopher, Intel Atom has not been seen for a long time, but it is. For the need for low-consuming, but nimble processors with time only increases in proportion to the increase in the number of various Internet. Intel’s new achievement in this path was the ULP (Ultra Low Power) architecture, which will find its application in several families of processor cores, including the one we are talking about today - Intel Tremont.







The new “like Atom” has become even more Core than before, because the emphasis is not only on improving the “performance / consumption” ratio, but also on the introduction of intelligent technologies, which previously did not visit this class of processor cores. In particular, branch prediction algorithms were borrowed from the top line.





Designed by Intel Tremont. Clickable



Other Intel Tremont features that directly affect performance:

• 6 instruction decoders with random execution,
• 10 executive ports
• dual loading / unloading conveyors,
• 4 cores in one module,
• L2 cache up to 4.5 Mb.

Intel Tremont Front End



A few more detailed words about the kernel frontend. As already mentioned, it uses a 32-byte L1 / L2 core class branch predictor with a long history. The random access system uses 32 KB of cache and processes 32 bytes per cycle. The x86 instruction decoding system consists of two clusters of 3 decoders each with unordered execution without a microoperation cache. If necessary (to save energy), a single-cluster scheme can be used.



10 actuators include an integer part of 7 ports with a large input window of extraordinary execution and parallel redundancy, as well as 3 vector ports with hardware encryption AES128 / SHA256 and support for an extended set of end-field instructions (Galois fields). By the way, it is worth recalling that the first Intel Atom models did not have an extraordinary performance at all. The memory subsystem includes 32 KB of data cache (three clock cycles to use) and an associative translation buffer (TLB) for 1024 entries, shared between code and data. L2 cache is split between 1-4 cores and can have a size from 1.5 to 4.5 MB



Now about the advanced technologies used in Tremont. These include:

• accelerator interface instructions - synchronization and task allocation for accelerators;
• Intel Speed ​​Shift - increased sensitivity when controlling the operating frequency;
• Intel Trusted Execution Technology and Intel Boot Guard - protection at boot time;
• Intel Total Memory Encryption - Protects memory contents from attacks.

Processors with Intel Tremont microarchitecture will be available next year. Previously announced that these cores will be included, including, in the composition of hybrid processors in combination with the "large" Sunny Cove cores.